Conventionally, a field programmable gate array (FPGA) has been known as an integrated circuit which can be configured to have a desired circuit by a customer or designer after manufacturing. As a technique of setting the circuit configuration in the FPGA, a technique is known that logically synthesizes a net list describing functions of a circuit to be designed by using a hardware description language and making a layout in the FPGA based on the net list at a gate level obtained by the logic synthesis. Then, after the circuit is configured in the FPGA, a processing of determining whether timing, area, power consumption, and so on satisfy predetermined constraints is performed.
The processing such as setting a circuit configuration in the FPGA and determining whether the constraints are satisfied is implemented, for example, by using an application program provided by the supplier of the FPGA. For example, the designer sets values to various parameters provided by the application program, and causes the application program to configure a target circuit in the FPGA. Values that can be set as the various parameters are provided in advance.
A related technique is disclosed in Japanese Laid-open Patent Publication No. 2005-174153 for designing a circuit including electrical wirings and optical connections. In this technique, an optical connection list and an electronic circuit connection list are formed by layout designing and evaluation of the electronic circuit, and then optical connections are designed based on the optical connection list, whereas the layout of electronic circuits is designed based on the electronic circuit connection list.
Another related technique is disclosed in Japanese Laid-open Patent Publication No. 2-162466 in which every time an input parameter for use for simulation is corrected, a correction process is stored into a storage device, and an input parameter is corrected by referring to the record of a correction process in which a relationship between a simulation result with a default value given to an input parameter, and a target output is similar to that for the input parameter to be corrected.
However, among values settable to parameters, it is difficult to set values to the parameters such that the performance of a target circuit can satisfy the constraints. For example, depending on the skill level of a designer, it is difficult for the designer to set an optimum value among multiple values to each parameter. Also, it takes time to set selected values to the parameters and then configure the target circuit in the FPGA. Thus, finding an optimum solution by repeating a process of sequentially setting each of multiple values for each of multiple parameters and then causing the FPGA to configure the target circuit until the performance of the target circuit satisfies the constraints is practically difficult as the number of combinations is enormous.
According to one aspect of the present disclosure, it is an object of the present disclosure to provide a design assistance program, a design assistance method, and an information processing apparatus capable of making it easy obtain a value from multiple values settable to each of parameters such that the performance of a target circuit can satisfy the constraints.